CV
Juliusz Frackowiak
Born in Gdansk, POLAND
Lives & works in Pomeranian district, POLAND
Education
2002 - 2007 Doctoral Study
Gdańsk University of Technology
Topic of doctoral study: Selective filtering of harmonic current with the current-voltage constraints of active power filter
1997 - 2002 Master of Science in Electrical Engineering
Gdańsk University of Technology
Master Thesis: “The Study of the Assembler Language Environment of the TMS320C6711 Digital Signal Processor”
1992 - 1997 Electronics technician
Technical School of Electronics
Experience
2017 - Senior FPGA MAG Applications Engineer
2006 - 2017 Senior FPGA/DSP developer, Power Electronics Devices Designer, Project Manager.
2002 - 2006 - Chief Engineer.
2002 - 2006 - Control system designer.
Grants & Awards
Honourable mention for very good academic results obtained in the academic year 2001/2002.
Skills
Designing of embedded control systems based on Altera/Intel FPGA and TI DSP devices.
Creating projects for FPGA devices in Quartus II environment from Altera/Intel.
Creating projects for TI C6000 DSPs.
Design of high-power Power Electronics devices, thermal simulations, developing control concepts, software development, commissioning and testing of control systems.
Publications
Analysis of continuous and discrete signals in a grid active power filter using simulation package SIMULINK – PTETIS 2005.
Fast frequency-to-digital processing - Targi Napędu i Elektroinstalacji, Gdańsk 2004.
Fast frequency-to-digital processing algorithm implemented in PLD structure for rotary-pulse transducers application - PTETIS 2004.
Efficient programming of the TMS320C6711 DSP using the SIMULINK package - PTETIS 2004.