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1MVA active filter in KŁODAWA S.A.
Design tasks
Design of control system
Design of Power units
Developing software for FPGA devices
Developing software for DSP devices
Device commissioning and testing
Design of control system
- System of functional modules
- High speed LVDS communication
- Altera/Intel FPGA based transmitters/receivers
- Main algorithm implemented in two C6000 DSP from TI
Design of Power units
- One phase of 3-level 1MVA voltage converter
- Design based on PrimePack3 IGBT Power Modules
Developing software for FPGA devices
- Dozens of Schematic Files
- Dozens of Signal Tap II Logic Analyzer Files
- Hundreds of lines in System Verilog
- Thousands of lines in Verilog
Developing software for DSP devices
- Over 16 thousand lines of code in C
- Application uses two DSPs
- Interrupt period of the embedded real time system 62,5us
Device commissioning and testing
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